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Release Date New Product
3/2017

COM-1806 Wideband signal capture and playback

The COM-1806 is a combine arbitrary waveform generator and data acquisition unit, equipped with 1GB or 8GB DDR3 memory

  • Files are transferred to/from a PC over gigabit Ethernet
  • I/Os from 1 to 64-bit at up to 125 MSamples/s
  • Simultaneous memory upload/download is possible
  • DDR3 memory throughput > 8 Gbits/s in each direction
  • Input signal conditioning: AGC, DC block, frequency translation, variable decimation, anti-aliasing filters
  • Output signal conditioning: variable interpolation, frequency translation, level control
  • File formats: binary or text tab-delimited (for simple interface with Matlab)
  • Connects directly to COM-4009 [0.4 - 4.4 GHz] RF modulator

2/2017

COM-4009 Digital to [400MHz-4.4GHz] broadband quadrature RF modulator

The COM-4009 takes 12-bit I/Q LVDS baseband input samples and translates the center frequency anywhere in the range 400 MHz to 4.4 GHz.

  • RF synthesizer step size 5KHz or less
  • Low phase noise (-82 dBc @ 1 KHz offset, 3 GHz)
  • Agile frequency synthesizer: 200us retuning. 8 stored frequencies
  • Measures output power and temperature
  • Internal VCTCXO or external higher stability 10 MHz frequency reference
  • Connects directly to COM-1800 FPGA development platform

10/2016

COM-7003 Turbo code error correction encoder/decoder

The COM-7003 is a full duplex turbo code encoder / decoder for error correction up to 16.5 Mbps (decoded bits) / 49.5 Mbps (encoded bits)

  • programmable rates from 1/3 to 6/7
  • programmable block length up to 2032 bits
  • Includes sync word insertion and automatic frame synchronization
  • CRC16 to discard decoded frames with remaining errors
  • Very low frame error rate: 1E-3 @ 1.6dB Eb/No (2032-bit frame, rate 1/3)

9/2016

COM-7003SOFT Turbo code encoder/decoder, VHDL source code & IP core

VHDL source code / IP core implementing turbo code error correction encoding and decoding

Flexible run-time configuration with programmable rate (from 1/3 to 6/7) and frame length (up to 1000 payload Bytes).

Pure VHDL source code for easy port to a variety of FPGAs.

12/2015

COM-1833 TDRSS modulator and channel simulator

The COM-1833 implements real-time modulation and channel simulation of a TDRSS user-to-ground link in four distinct blocks, each with distinct parameters controls:

  • TDRSS customer modulator, including spread-spectrum and narrow-band PSK
  • TDRSS transponder induced distortions
  • Ground terminal induced distortions
  • Orbit dynamic effects
It interfaces with COM-1826 TDRSS Spread-spectrum receivers over GbE LAN.

8/2015

COM-1931 L/S-band burst spread-spectrum transceiver

L/S-band modem to send and receive short UDP frames over wireless, satellite or cable

Direct-Sequence Spread-Spectrum (DSSS) modulation

Nominal frequency of operation: 950 2175 MHz for direct connection to external LNB or BUC. Customization to other frequency bands is possible

Burst mode operation: fixed-length 512-bit data frames from/to LAN/UDP ports. Multiple frames transmitted efficiently with only 32-symbol separation.

7/2015

COM-1831SOFT Burst-mode DSSS modem up to 80 MChips/s

VHDL source code / IP core implementing a burst-mode spread-spectrum modem

The COM-1831SOFT is a burst-mode direct-sequence spread-spectrum modem for transmitting and receiving UDP data frames over a wireless or cable medium. It not only includes the DSSS modulation and demodulation functions, but also ancillary functions such as error correction, internet protocol stack and Ethernet MAC

The chip rates, symbol rates, spreading Gold code, and center frequency are fully programmable at run time. Several other generic parameters allow one to customize the code for the target application. Frame length, frequency acquisition range, acquisition threshold, preamble length, number of parallel code search circuits are all adjustable prior to code synthesis

Pure VHDL source code for easy port to a variety of FPGAs

4/2015

COM-1510SOFT Block mode convolutional FEC codec

VHDL source code / IP core implementing block-mode error correction encoding and decoding

Flexible run-time configuration. Trade-off high-speed parallel processing versus small size sequential processing. GMR-1 3G compatible. Pure VHDL source code for easy port to a variety of FPGAs.

See also In the works!