Overview
- Single-speed 10 Gigabit Ethernet Media Access Controller(MAC) for implementation on low-cost FPGAs.
- Very low latency: 25.6ns
- PHY interface:
- Standard XGMII interface for compatibility with off-chip PHY device or internal IP cores using the XGMII interface
- Tested with Xilinx 4-lane XAUI free core to external PHY on Artix lowest speed device
- Compatible with Xilinx 10 Gigabit Ethernet PCS/PMA (10GBASE-R) IP core
- Application interface: simple flow-controlled 64-bit interface synchronous with 156.25 MHz clock
- Transmit pause through MAC control messages
- VLAN-aware (i.e. IEEE 802.1Q conformant)
- Compatible with Jumbo frames. User can set the MTU frame lengths for the transmit and receive paths
- Automatic:
- Preamble generation and removal
- 32-bit CRC generation and checking
- Payload padding for very short transmit frames
- VHDL source code included. Portable to any FPGA target capable of 156.25 MHz clock.
Documentation
Specifications
Complete VHDL/IP Core license agreement
Related products
IP/UDP/TCP servers/DHCP server stack, VHDL/IP Core
IP/UDP/TCP clients/DHCP client stack, VHDL/IP Core
Other network IP cores
Development platform FPGA + GbE LAN
10G Ethernet network interface