Overview
- High-speed LDPC rate 7/8 error correction codec
- This codec operates in block mode, whereby a fixed-length frame is encoded and decoded: 7136-bit uncoded, 8160-bit coded
- Includes encoding, decoding, frame synchronization and data randomization
- Maximum decoder throughput is typically in the range 50 – 400 Mbits/s depending on the FPGA technology and operating Eb/No. Maximum encoder throughput is greater than 1 Gbits/s.
- Compliant with CCSDS 131.0-B-3 Blue Book, section 7.3
- Decoded bit error rate < 8.7E-8 @Eb/No=3.9 dB
- Decoded frame error rate < 1E-5 @Eb/No=3.9 dB
- VHDL source code included
Documentation
Specifications
Complete VHDL/IP Core license agreement
Related products
Other error correction IP cores