Overview
- Encoded frame sizes: 16200, 32400, 64800 bits
- User programmable frame size, coding rate, VL-SNR puncturing and shortening, maximum number of decoding iterations
- Includes encoder, decoder, BER tester, PRBS11 test sequence generator
- Maximum decoder throughput is typically in the range 50 – 400 Mbits/s depending on the FPGA technology, threshold Eb/No, number of parallel decoders. Maximum encoder throughput is greater than 1 Gbits/s.
- Compliant with ETSI EN 302 307-1 V1.4.1 (2014-11) (DVB-S2) and . ETSI EN 302 307-2 V1.1.1 (2015-02) (DVBS2X)
- Typical Bit Error Rate / Frame Error Rate for rate 1/2 nldpc = 16200: BER < 10-7 FER < 10-4 @ Eb/No = 0.9 dB
- Tradeoff device utilization vs throughput: select 45 or 360 parallel decoders prior to synthesis
- VHDL source code included
Documentation
Specifications
Complete VHDL/IP Core license agreement
Related products
Other error correction IP cores