Overview
This SOQPSK modem is written in generic VHDL.
The entire VHDL source code is deliverable. It is portable to a variety of FPGA targets
- SOQPSK is a spectrum-efficient constant envelope modulation well suited for operation through power amplifiers near saturation.
- Flexible programmable features:
- Symbol rate up to fclk/4, where fclk is the processing clock frequency
- SOQPSK-MIL and SOQPSK-TG
- Excellent BER performance using trellis decoding (SOVA)
- 4-bit soft-decision demodulator output for best FEC decoder performance
- Performance:
- Near theoretical BER vs Eb/No
- ±50ppm symbol timing tracking
- Carrier frequency acquisition: ±10% of symbol rate at the threshold
- Acquisition threshold < 2dB Eb/No
- Provided with IP core:
- VHDL source code
- Matlab .m file for generating stimulus files for VHDL simulation of the demodulator and for end-to-end BER performance analysis at various signal to noise ratios
- VHDL testbench (stimulus file input, or back-to-back modem)
- BER tester
Documentation
Specifications
Complete VHDL/IP Core license agreement
Related products
Other modem IP cores
Ready-to-use digital CPM modem
Ready-to-use RF CPM modem