Overview
- High-speed BCH block code encoder and decoder for FPGAs
- Fully compliant with the DVB-S2 standard ETSI EN 302 307
- VHDL source code portable to most target FPGAs
- Parallel I/Os and processing for high-speed operation:
- 2.7 Gbits/s encoding [Xilinx Ultrascale+ -1 speed grade]
- 1.5 Gbits/s encoding [Xilinx Artix7 -1 speed grade]
- up to 1.7 Gbits/s decoding [Xilinx Ultrascale+ -1 speed grade]
- up to 886 Mbits/s decoding [Xilinx Artix7 -1 speed grade]
- Corrects t = 8, 10 or 12 errors per block
- Decoder flags frames with uncorrectable errors
- Decoder reports number of bit errors corrected at the end of each decoded block
- Built-in test tools:
- PRBS-11 test sequence generation
- BER measurement
- License price includes limited but generally sufficient technical support
Documentation
Specifications
Complete VHDL/IP Core license agreement
Related products
Other error correction IP cores