Overview
- Portable VHDL source code for Turbo Code error correction encoder and decoder .
- Flexible dynamic (i.e. at runtime) user-selected configuration:
- Block length up to 8000 bits
- Puncturing patterns for rates 1/3, 1/2, 2/3, 3/4, 4/5, 5/6, 6/7, 7/8
- Frame error rate (FER) example: 2032-bit frame, Rate 1/3, 5-bit soft quantization, 15-iterations
- FER = 10-2 @ Eb/No = 1.4 dB
- FER = 10-3 @ Eb/No = 1.6 dB
- Frame error rate (FER) example: 472-bit frame, Rate 1/2, 5-bit soft quantization, 15-iterations
- FER = 10-2 @ Eb/No = 1.9 dB
- FER = 10-3 @ Eb/No = 2.2 dB
- VHDL source code included.
Documentation
Specifications
Complete VHDL/IP Core license agreement
Related products
Other error correction IP cores
Development platform FPGA + GbE LAN