Overview
- Code rates 1/2, 2/3, and 4/5
- This codec operates in block mode, whereby a fixed-length frame is encoded and decoded: Information block lengths k: 1024, 4096, 16384 bits
- Includes encoding, decoding, frame synchronization and data randomization
- Compliant with the AR4JA codes specified in CCSDS 131.0-B-3, Blue Book, section 7.4, 9, 10. Compliant with IRIG standard 106-15 Appendix R.
- Typical Bit Error Rate / Frame Error Rate for rate 1/2 k=4096: BER = 10-6 FER = 1 10-5 @ Eb/No = 1.35 dB
- Throughput: Encoding: > 100 Mbits/s Decoding: [0.46-0.99]* FPGA clock frequency @ 10-5 BER
- VHDL source code included
Documentation
Specifications
Complete VHDL/IP Core license agreement
Related products
Other error correction IP cores