Overview

• High-speed Reed-Solomon error correction codec
• This codec operates in block mode, whereby a fixed-length frame is encoded and decoded
• Includes encoding, decoding, frame synchronization, interleaving (CCSDS or DVB) and data randomization
• Maximum decoder throughput is typically in the range 0.58 – 1.3 Gbits/s (coded bits) depending on the FPGA technology and code selection
• Runtime configuration selection:
• Intelsat standard (IESS-308): sync word 5A0FBC66, (225, 205, 10), (219, 201, 9), (194, 178, 8), (208, 192, 8), (126, 112, 7)
• CCSDS standard (131.0-B): sync word 1ACFFC1D, I interleaved blocks, (255,223,16), (255,239,8)
• DVB standard (ETS 300 421): (204, 188, 8)
• Other commonly used (N,K,t) RS configurations: (80, 56, 12), (255, 233, 11), (66, 52, 7)
• Corrects all Byte errors up to t, for a (N,K,t) code, as per theory
• VHDL source code included

Documentation

Specifications
Complete VHDL/IP Core license agreement

Related products

Other error correction IP cores

Buy

$550 COM-1807SOFT encoder

$650 COM-1807SOFT decoder

$1100 COM-1807SOFT encoder + decoder bundle