Overview
- Bi-directional error correction encoder/decoder, including:
- Convolutional encoding/Viterbi decoding
- V.35 scrambling/descrambling
- Serial HDLC framing/deframing
- Convolutional codec with selectable rate and constraint lengths:
- K = 5, rate 1/7
- K = 7, rates 1/2, 2/3, 3/4, 5/6, 7/8
- K = 9, rates 1/3, 1/2, 2/3
- Maximum encoded output and coded input rates: 120 Mbps (for K=5, 7), 90 Mbps (K=9) (Xilinx Spartan-6)
- Differential decoder to resolve bit stream inversion
- 4-bit soft-quantized or 1-bit hard decision coded input
- Built-in test tools:
- PRBS-11 test sequence generation
- BER measurement (coded, decoded)
Documentation
Specifications
Complete VHDL/IP Core license agreement
Related products
Other error correction IP cores