Error Correction Codec 120Mbits/s
KEY FEATURES
  • Bi-directional error correction encoder/decoder, including:
    • Convolutional encoding/Viterbi decoding
    • V.35 scrambling/descrambling
    • Serial HDLC framing/deframing
  • Convolutional codec with selectable rate and constraint lengths:
    • K = 5, rate 1/7
    • K = 7, rates 1/2, 2/3, 3/4, 5/6, 7/8
    • K = 9, rates 1/3, 1/2, 2/3
  • Maximum encoded output and coded input rates: 120 Mbps (for K=5, 7), 90 Mbps (K=9)
  • Differential decoder to resolve bit stream inversion
  • 4-bit soft-quantized or 1-bit hard decision coded input
  • Built-in test tools:
    • PRBS-11 test sequence generation
    • BER measurement (coded, decoded)
  • Connectorized 3”x 3” module for ease of prototyping. High-speed 98-pin PCIe connectors (left, right). Single 5V supply with reverse voltage and overvoltage protection. Interfaces with 3.3V LVTTL logic.
    • block diagram

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    COM-1509
    Turbo Code
    DVB-S2 long BCH code (IP)
    Documentation
    Specifications (182 KB)
    Schematics
    $295 Ready-to-use Module
    $750 IP core, VHDL source, unlimited use