COM-1200 FPGA Development Platform (Spartan-3 2000) & Tx/Rx Analog

KEY FEATURES

Develop custom signal processing applications on FPGA using this generic development platform

Xilinx Spartan-3 XC3S2000-4 FPGA features 2 million system gates, 720Kbit of dual port memory, 40 dedicated 18x18 multipliers

Analog front end (AD9860) features:

• 2 10-bit high-speed ADCs 64Msamples/s
• 2 12-bit high-speed DACs 64Msamples/s ^[1]
• 2 10-bit ADCs and
• 3 8-bit DACs

USB 2.0 interface supports signaling rates of 480 Mbits/s (High Speed) and 12 Mbits/s (Full Speed). Typical sustained data throughputs are 85 Mbit/s (HS) and 6.5 Mbit/s (FS)

Temperature sensor

32Mb non-volatile flash memory stores up to 4 distinct FPGA configurations (3 custom + 1 fixed baseline). The selected configuration is automatically reloaded at power up or upon command within 2.2 seconds

Graphical User Interface is used for remote monitoring and control over USB. This includes loading FPGA configuration file into flash (non-volatile). FPGA configuration can also be loaded via a JTAG cable (volatile)

This module is interface compatible with other pre-programmed ComBlock modules

120 MHz maximum practical FPGA processing clock rate (typ.)

ComScope–enabled: key internal signals can be captured in real-time and displayed on a host computer

Connectorized 3”x 3” module for ease of prototyping. Standard 40 pin 2mm dual row connectors (left, right, bottom). Single 5V supply with reverse voltage and overvoltage protection.

Includes NGC components (software drivers) for USB 2.0/1.1 and AD9860 mixed-signals front-end

ComBlock COMPATIBILITY LIST

Analog I/O
COM-3501 UHF transceiver
Digital Input
Most Comblocks
COM-3501 UHF transceiver
COM-3001/2/3/4/5/6/7/8/9/10 RF/IF/Baseband receivers
COM-8001 Arbitrary waveform generator, 256MB/1GB, 40 Msamples/s
Digital Output
Most ComBlocks
COM-8002 High-speed data acquisition. 256MB/1GB, 40 Msamples/s
Baseband Interface
COM-5003 TCP-IP / USB gateway
COM-1200/1300/1400 FPGA development platforms

^[1]128 MSamples/s after fixed x2 interpolation