COM-1807SOFT Reed-Solomon FEC decoder, VHDL Source / IP core

Reed-Solomon FEC decoder, VHDL Source / IP Core
Supports for the following standards:

• Intelsat (225,205,10), sync word 5A0FBC66
• Intelsat (219,201,9)
• Intelsat (194,178,8)
• Intelsat (208,192,8)
• Intelsat (126,112,7)
• CCSDS (255,223,16) sync word 1ACFFC1D
• CCSDS (255,239,8)
• DVB (204,188,8)
• code (80,56,12)
• code (255,233,11)
• code (66,52,7)

Includes ancillary functions such as elastic buffer (input, output), sync marker detection, de-interleaving, de-randomization.
Number of interleaving blocks 1,2,3,4,5,8
Standard VHDL code is portable to most target FPGA and vendors.
Unlimited license to make and use. See the complete licensing terms at comblock.com/download/softwarelicense.pdf